Hardware Design and Development

[TerryJC]

plus there is a slight flicker on the Screen at Position 2.

It looks like we have a faulty Screen, or at least one that is more susceptible to interference than the others. On one occasion the screen did not display anything but otherwise is appears to be OK at first, but after a few minutes operation the image begins to flicker and this flickering gets progressively worse. The other three Screens appear to be OK, including when plugged in to the same position.

Whatever it is that is failing would appear to be related to suppression of EMI. When I shut the Pi down, the interference persists until the Pi has completed all activity. At this point the Pi still has power applied, but the Monitor has gone into shutdown because it has lost the signal from the Pi. I believe that I have confirmed this in principle by booting the Pi with the Monitor and keyboard disconnected. I then started the software using SSH and there was no sign of flickering for a considerable period (at least 10 minutes). Flickering then started; initially as an odd extra line and then gradually it got worse. This time, when I shut down the Pi the flickering persisted until I turned off the power. I think that this proves that the susceptibility increases steadily after power is applied, so at first it is negligible and then it picks up high amplitude interference from the Monitor (possibly the adaptor which is quite close), but eventually it reacts to interference from the Pi itself.

Penri,

How many OLED Displays did you buy? I thought you said seven, but I can only account for six at the moment. I have five here and I gave one back to you a while back, Should there be another?

I still cannot get the Screen at Position 4 to work, so that's my next job.

[Penri]

Those waveforms look nice an clean!
Good bit of investigative work.

[Penri]

Terry

I have two here, the one you returned and one I kept as a physical reference.

Penri

[TerryJC]

I have two here, the one you returned and one I kept as a physical reference.

Thanks. I thought I'd lost one.

[TerryJC]

I hate to give up on anything, but I cannot see why the fourth Screen in my implementation won't work. I can reliably render images on Screens 1, 2 and 3, but absolutely nothing is displayed on Screen 4; it just remains blank.

I have monitored the signals at the screen input pins, swapped screens between positions and also modified the software to ensure that the Screen is properly addressed (I was concerned about floating inputs during Initialise). All to no avail. When the program is executed, the Screens are all initialised using code that I culled from the Examples; this is seen on the working screens as a 'speckled' raster, which is then cleared by the next command. There is no sign of life from the fourth screen, whether it is installed together with the other three or on its own.

I've run out of ideas. Perhaps if I sleep on it something might come to mind.

I've just remembered. Screen 4 didn't work on my first prototype although that was a mess, so that doesn't necessarily signify.

[hamishmb]

Do you see the initialisation "speckled" pattern on the 4th screen?

If you like (and can point me to the relevant code), I will take a quick look at the software side of things in case I see any glaring errors.

[TerryJC]

Do you see the initialisation "speckled" pattern on the 4th screen?

No nothing.

If you like (and can point me to the relevant code), I will take a quick look at the software side of things in case I see any glaring errors.

See attached.

[TerryJC]

I just remembered that the underlying driver and / or config code may ask for something I haven't included; if so, let me know.

[TerryJC]

With no new ideas forthcoming to solve the problem with Position 4, I think my next step should be to build a second Prototype / 1st-Off Production assembly to exactly the same design (electrically) as the current one.

When I say 'exactly the same design' it will be virtually identical in terms of the circuit, but I will adjust the layout slightly to shorten the length of the parallel tracks carrying the common signals. This will mean reducing the gap between connectors by one row so that I have more room at the bottom of the board. I will then put the 1 k resistors and 220 pF capacitors at the extreme end of the tracks, instead of as they are in the current layout (see viewtopic.php?p=4389#p4389.

Penri,

Have you any thoughts on this?

[TerryJC]

I have re-designed the Veroboard as outlined above. Attached is the new layout and a slightly updated Circuit Diagram which has had a minor change to the pin numbering.

I'll be starting the new build later today.