Hardware Design and Development

This forum is to cover discussion about the design and implementation of a model TV Set to be placed in the Window of one of the two TV Shops in the WMT.
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

It's taken me a while, but I have now completed the new design with Bus Buffers (see attached).

As anticipated, this has done nothing for the Screen at Position 4; I still can't get a flicker out of it. However, you may recall that the last iteration of this Prototype couldn't display on any more than two Screens at a time; this version seems to work fine with three Screens at a time.

One of the reasons it has taken me so long to get here is that I tried another idea out before I redesigned and modified the latest version. It occurred to me that the longest signal path is in the Screen wiring itself (on the previous Prototype there was about 100 mm of wire between the Pi GPIO Pin and the top of the connectors, 40 - 50 mm from Position 1 to Position 4, and 200 mm of wire to the Screen. I therefore made a 'fake' DIL network resistor of four 1 k resistors, commoned at one end, on a small piece of Veroboard. I then soldered the Veroboard to the Screen using Header Pins in the second set of terminals on one of the Screens. (I chose 1 k because that would load each pin to 53 mA if four Screens were connected and the absolute maximum for the Pi is 54 mA.)

It didn't work, so I continued with the buffered version, with the results detailed above.

Notwithstanding that, it occurs to me that using DIL Network resistors might provide a way to extend the wiring on site. If I've understood the Data Sheet correctly it would appear that each driver in the CD74HC367E is capable of 20 mA, which is a bit more than the Pi, so we could use 680 Ohms at each Screen to terminate the buses. This would give us nearly 5 mA flowing to each pin on each Screen, which is probably a lot more than we have now. I don't think that would make the fourth Screen burst into life, but it would probably add to the reliability (in terms of working, not faults) when we have to use long wires.

Penri,

Any thoughts on the above?

If we decide to adopt the terminating resistors, I'd like to buy some 'proper' DIL devices because it takes ages to make each fake one.
Attachments
Tiny_TV_Veroboard_Layout_V07.odg
(1.72 MiB) Downloaded 61 times
WMT_Tiny-TVs_Interface_Circuit_Diagram_V0.7.odg
(52.5 KiB) Downloaded 62 times
Terry
Penri
Posts: 1284
Joined: 18/05/2017, 21:28

Re: Hardware Design and Development

Post by Penri »

Terminating the lines at the screens would seem a good option to pursue, given experience thus far.

As a thought / discussion point instead of a resistor between the data line and deck what about a balanced arrangement with two resistors in series between the +ve supply and deck with the data line at the mid point, sketch attached.

The CD74HC367E has source and sink O/P transistors so it would actively drive the line high of low.

Any view?
Attachments
line termination.odg
(12.27 KiB) Downloaded 63 times
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

I did wonder about the totem pole design of the Bus Buffers. The problem is I'm still short of real estate so if we want to do this we would have to compromise a bit on how it is done physically.

Using the network resistors at the Screens to terminate the active lines to 0 V is easy because a five resistor DIL pack with a common line fits nicely between 0 V and the active pins (DIN, CLK, CS and DC). The RST line is not used and the NC line gets a resistor it doesn't need. To do a balanced version of this wouldn't be so simple, I'd have to use two DIL Resistor packs and a small piece of Veroboard to configure them.

Of course I could easily set up the balanced terminations at the connector, but one set for all screens and only for the DIN and CLK lines (which is what is there at the moment in the unbalanced form.

Another thought. It is possible that the Pi itself has a totem pole O/P on it's driver (the Peripherals Spec only shows a block diagram of the GPIO Pins). If so, it may have been that we needed a balanced terminator all along.

I think that the DC and CS lines are too slow to need terminators, I only added them to the remote version at the screens because I could. I'll add a couple of 1 k resistors to the Veroboard this afternoon to see if that makes the fourth Position burst into life.

In the meantime, what do you think is the best approach?
Terry
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

I added the two 1 k resistors between the 3.3 V line on Position 4 and CLK and DIN. There was no discernible difference; Positions 1 to 3 worked fine but nothing at Position 4.

That doesn't mean of course that we shouldn't use balanced terminators, and I'm thinking that if we removed the Position 4 connector and associated components, I'd have room for four Resistor Packs, two to 0 V and 2 to 3.3 V. The only small problem with that is that each connector has its own separate 3.3 V PSU regulator, so I would either have to pick one of those or maybe (perhaps better) use the 3.3 V from the Pi.

The above solution kind of precludes the terminators being at the Screens, unless we split the terminating resistors between the connectors end and the Screens.

Penri, Any further thoughts or preferences?
Terry
Penri
Posts: 1284
Joined: 18/05/2017, 21:28

Re: Hardware Design and Development

Post by Penri »

I was contemplating putting a terminating resistors on a small veroboard at the screen end, I'll accommodate them in the TV enclosure.

As each screen's supply is referenced back to a common 0V the driver should not complain about the slight differences between it's 3V3 supply and the screens supply.
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

Ok. I'll get some Resistor Packs. Even if we only have three Screens per Pi, we would still need 72 discrete resistors or 36 if we only terminated the two fast pins.
Terry
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

I had to get 1 K resistor Packs because the cheapest 680 Ohm ones I could find were £1 each. I've got 40 1 k ones in packs of five for just over a fiver.

I'm sure that the slight reduction in current won't matter.
Terry
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

The Resistor Packs arrived yesterday and I have now completed the design and construction of four Terminator Boards. The good news is that the first three Positions still work OK, but as expected, the fourth Position is still dead.

I have attached the latest Circuit Diagram, Main Veroboard Layout and Terminator Board Layout.

I will now concentrate on the software.
Attachments
WMT_Tiny-TVs_Interface_Circuit_Diagram_V0.8.odg
(53.72 KiB) Downloaded 64 times
Tiny_TV_Terminator_Layout_Detail.odg
(89.8 KiB) Downloaded 62 times
Tiny_TV_Veroboard_Layout_V08.odg
(1.72 MiB) Downloaded 63 times
Terry
Penri
Posts: 1284
Joined: 18/05/2017, 21:28

Re: Hardware Design and Development

Post by Penri »

Terry

For your information, in addition to the 3D printed TinyTV chassis, I have, at last, got movement on the build of 2 TV lounges for the King's Head and Crown Hotels plus kicked of re-modelling of the Holman's shopfronts and the Wimborne Radio interior all with the possibility of installing TinyTVs. Planning and executing the plan, with any degree of surety, under the current circumstances it far from easy so implementation has to remain flexible, just so I know can you let me know how you stand with the TinyTV control H/W and S/W, please?

Penri
TerryJC
Posts: 2616
Joined: 16/05/2017, 17:17

Re: Hardware Design and Development

Post by TerryJC »

Penri,

I put the build on hold while I worked on the Minster re-engineering, but it can be restarted if need be. I have one complete unit, with software that works (it can easily be tweaked if need be). Hopefully the software for the Minster re-engineering will be completed within a week or two and then I will finalise the internal wiring to the external connectors.
Terry
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