Hardware Design and Development

[TerryJC]

I'll do the tests tomorrow. I have 10 n, 1 pF and 20 pF (the smaller values arrived today.

[Penri]

I can probably find some intermediate values in the "other capacitors" pile if the initial results look promising.

[TerryJC]

It may give us some more info. if we can see which signal is in the sync. with the noise

Can you display the the scope:
The 3V3 noise and the MOSI together on the screen
The 3V3 noise and the CLK

Penri,

Two quick tests before I start stripping capacitors from the board:

3V3 noise and the CLK

Tiny_TV_3_3_and_CLK_Line_During_Render.JPG (209.54 KiB) Viewed 665 times

Notice that the CLK line is pretty noise free (if we expanded the Y-axis, we would see the overshoot that we noticed earlier).


3V3 noise and the MOSI

Tiny_TV_3_3_and_MOSI_Line_During_Render.JPG (207.8 KiB) Viewed 665 times

In this case, there appears to be a 'gulp' of current on the MOSI Line, in sync with the 3.3 V Line, even when it is not active.

The thing is that the major noise on the 3.3 V line is not in sync with any of the real SPI Bus signals; it is there all the time once the screen has rendered, whether or not the CLK and MOSI Lines are active. I feel that this noise is effectively generated within the Screen electronics as it refreshes the display at a 100 Hz rate.

Quite why it needs to refresh the display I don't know. I would have thought that it would simply need to brighten the relevant pixels and then leave it as it is. This behaviour is more reminiscent of a CRT.

I'll see what I can find out about how these OLED Displays work.

[TerryJC]

Quite why it needs to refresh the display I don't know. I would have thought that it would simply need to brighten the relevant pixels and then leave it as it is. This behaviour is more reminiscent of a CRT.

I'll see what I can find out about how these OLED Displays work.

Just after I submitted that posting, the penny dropped. Normally, screens are not displaying static images; they are being used to show videos, etc. It would be possible to only change the display when new data came in, but I expect that they don't actually do that. The circuits to receive the image information over the SPI or I2C Bus work standalone and simply write the decoded pixel data to video RAM. The circuit to render the image also works standalone and simply re-renders whatever is in video RAM at a 100 Hz duty-cycle. So the current needed to light each pixel will change as the display is scanned; in particular the Andy Pandy image has a fair bit of grey and some big areas of black. This is why the All-Black, All-White and Grey images didn't produce such massive spikes.

I have one or two things to do this morning, but then I'll get back onto this later today.

[TerryJC]

I had a brainwave! I began to consider why the big gulps of current were showing up on the scope; these waveforms were presumably being developed across the big electrolytic, so if that wasn't there how would the current gulps manifest themselves? I therefore took all of the capacitance off the board and ran the Andy Pandy render again.

With a scope timebase of 10 ms

Tiny_TV_3_3_Line_During_Render_No_Capacitance_1.JPG (191.66 KiB) Viewed 665 times

Notice that the 100 Hz content has disappeared completely and the amplitude of the spikes has tripled.

With a scope timebase of 250 us

Tiny_TV_3_3_Line_During_Render_No_Capacitance_2.JPG (197.01 KiB) Viewed 665 times

Now the dominant frequency can be seen as 40-50 kHz in the spikes. I reckon if I now start putting low value ceramic capacitors across the 3.3 V line, I have a fighting chance of suppressing the spikes without resurrecting the 'gulps'.

[TerryJC]

Quick Sitrep:

So I first tried putting the 10 nF capacitor back across the 3.3 V Line and it certainly helped in terms of the amplitude of the spike. However, a very small 'gulp' became apparent. I tried 220 pF and that didn't introduce the gulp, but it didn't do too much for the spike amplitude either. I then tried a 100 nF capacitor and this, predictably, reduced the spikes but more gulp appeared.

So far I've focused on reducing the noise on the 3.3 V line. Tomorrow I'll look into whether I can now drive two displays from the same PSU without noise on the screen. If we can, then maybe we can drive four screens. If not, then perhaps four independent 3.3 V lines would do the trick, That would need four regulators, but no electrolytic capacitors so there should be sufficient real estate on the board.

[Penri]

Hummm you've made some very interesting discoveries here but I wish I could explain them. Perhaps better to concentrate on controlling the undesirables and creating a working circuit. Very impressive work.

[TerryJC]

Some progress at long last! It's of the nature of two steps forward and one back (as opposed to one step forward and two back as with previous progress), but ii is positive progress at long last.

Today I removed all capacitors in the 3.3 V circuits and connected a screen to each connector in turn (one at a time). All positions worked except No 4 (I'll come back to that). I then connected two screens; one to Position 1 and one to Position 2. Both screens worked but with a great deal of noise displayed. I then connected one screen to Position 1 and one to Position 3. Still noisy.

I then added a 1 k resistor between MOSI and 0 v and between CLK and 0 V. Both screens worked but this time with no noise at all! (I haven't added the low value capacitor yet, but that didn't seem to be needed.)

I've just spent some time trying to debug Position 4, but so far without success. All pins appear to be carrying the correct waveforms but the display simply doesn't do anything. I measured the signals on the display itself to isolate any problems with pins not mating.)

So from this I can say that we should be able to display different images on up to three screens and if I can work out why Position 4 isn't working, then we could make it to the goal of four.

Tomorrow I am going to add a third and fourth 3.3 V regulator to the board plus the slugging caps on the MOSI and CLK lines. If the fourth position still doesn't work, then I think that the length of the wiring plus tracks will be the problem, but I can't see why given that the signals appear to be identical to the ones on the other three positions.

[TerryJC]

I've done half the work that I said that I would do yesterday; I've added the slugging caps to CLK and MOSI. Acting on a hunch, I used 220 pF again and this time the Screen at Position 1 didn't stop working. I suspect that having 1 k and 220 pF on the CLK line and nothing on the MOSI Line was sufficient to put the CLK and MOSI out of sync enough to prevent the data from being properly received. (The time constant is 220 ns and the clock is active for 250 ns.) Below is the current situation:

CLK and MOSI with Both lines terminated with 1 k and 200 pF

Tiny_TV_CLK_and_MOSI.JPG (225.58 KiB) Viewed 655 times

It is clear that there is crosstalk between these two lines, but not enough to cause any problems. These measurements were taken across the capacitors at the end of the lines.

These changes didn't cause the Screen at Position 4 to burst into life, so now I'll add the additional regulators and see what happens.

[TerryJC]

I now have four 3.3 V Regulators feeding four isolated Position connectors. The good news is that Positions 1,2 and 3 now render properly. The bad news is that Position 4 is still dead plus there is a slight flicker on the Screen at Position 2. The circuit and layout diagrams for the current build are attached.

Tomorrow, I'll have one last try at diagnosing Position 4 and also see where the noise on Position 2 is coming from. It may be time to start putting caps back into the 3.3 V circuits, now they are all isolated